June 19 - 23, 2016
8:00 AM (Local Time / Amsterdam / Berlin / Bern / Rome / Stockholm / Vienna)
Hear our experts explain details around debugging and performance analysis as it relates to high performance computing.
At this year's ISC High Performance event, two of our experts will be addressing different situations related to debugging HPC systems and code.
- Presenter: Dr. Nikolay Piskun
- When: Sunday, June 19, 2016, 2:00 p.m. - 6:00 p.m.
- Title:Debugging & performance analysis on native & offload HPC architectures
Abstract: Modern hybrid architectures, with GPUs and coprocessors, have more complexity than ever before. On top of that, there is an increasing number of programming models available. The developers of simulation codes have to deal with the intricacies of these environments in order to obtain correct code that achieves the performance offered by these platforms. Proficiency with debugging and profiling tools can help developers deal with this complexity.
This tutorial is targeted to application developers and HPC professionals that need to understand how these tools can help them to achieve their goals quicker and more effectively. We cover debugging techniques on these architectures using the TotalView parallel debugger. We also discuss profiling tools for GPUs and coprocessors. Here the training focuses on commercial (vtune, nvprof) and open source (extrae/paraver) tools.
The usage of these tools will be demonstrated using OpenMP 4.0 and OpenACC plus MPI examples, due to the increased popularity of these models. These demonstrations will show both offloading capabilities of NVIDIA GPUs and native executions on Intel Xeon Phis covering the most critical models in HPC today. Additionally, a POWER8+GPU system will also be used as part of the demonstrations and explanations.
- Presenter: Martin Bakal
- When: Tuesday, June 21, 2016, 5:40 p.m.
- Title:Debugging code written for many-core Xeon Phi architecture
Abstract: Stop by the Intel booth to hear our dynamic analysis product manager, Martin Bakal, talk about debugging code that is written for a many-core Xeon Phi architecture.
Learn more about the conference at the ISC High Performance 2016 website.
If you'd like to talk HPC, enterprise-scale dynamic analysis, debugging, and more, stop by and view the presentation or set up a meeting with Marty in advance to talk about what's new with our dynamic analysis products, TotalView for HPC and CodeDynamics.